Next-generation field effect transistors (FETs) require aggressive scaling of device dimensions to reduce device delays, access resistances, and parasitic capacitances for improved high-frequency performance. In particular, ultra-short nanometer-scale gate length and source-drain spacing are required in a robust, high throughput, reproducible, and reliable process.
Conventional, fabrication techniques for high-frequency FETs (and particularly for HEMTs) use e-beam lithography, metal evaporation and lift-off for forming a T-shaped gate structure. However, the aspect ratio (defined by the ratio of height and length of the gate foot, =h/Lg) of lithographically-defined gates is limited, decreasing the gate head-to-channel distance and giving rise to parasitic capacitances in the devices fabricated using this prior art technique. Furthermore, device uniformity, yield, and minimum gate length relies on alignment accuracy and resolution of e-beam lithography tool, limiting minimum dimensions of scaled devices.